Artificial intelligence (AI) will trigger memory testing requirements. Mobile phone computer is developing rapidly, and deep learning (Deep learning) has been growing rapidly. It has changed the way that computers watch, listen and recognize things in the real world, and gradually apply them to smart phones, wearable devices and autonomous driving vehicles. AI At present, many chip suppliers are increasingly interested in deep learning, which also means that the demand for memory of system single chip (SOC) will increase greatly, which will drive the demand for memory testing.

Deep learning can help the computer understand image, sound, text and other data, imitate the operation mode of neural network, and analyze the characteristics of the picture with multi node and hierarchical operation. The nodes in the lower layer only calculate the black-and-white contrast on each pixel, while the nodes in the second layer distinguish lines and boundaries with continuous contrast according to the data in the first layer. As the level becomes higher and higher, the accumulated calculation information becomes more and more complex, You can identify and classify the pictures.

For the semiconductor industry, deep learning will be applied to various fields in the future. Convolutional neural network (CNN) is widely used in the field of image and video recognition. This also means that SOC's demand for memory will increase greatly and its importance will also increase relatively; Undoubtedly, the large amount of data not only requires a huge memory storage space, but also brings more challenges to the memory test of SOC.

Thick wing technology pointed out that there are three main directions for testing SOC, namely traditional function test, structure test and self-test (BIST). Functional testing can only be performed by a group of testing machines alone. When SOC becomes more complex and uses more memory, more simple and accurate memory testing function is required.

Worried about the increasing efficiency and cost of the testing machine in the future, semiconductor manufacturers began to add more scanning paths to the design, so as to find out the potential errors in the manufacturing of the chip by means of structural testing, so that there will be more and more BIST integrated with SoC design.

However, although BIST can successfully reduce the product defect rate (DPPM) and company cost, it will also affect the chip efficiency. In this regard, Houyi technology has specially developed a memory self-test circuit generation software called "brains", which starts from the overall chip design, fully automatically interprets and groups the memory, so that users can easily generate optimized BIST circuits, greatly improve the test yield and reduce the test cost from the front end of product design. This software architecture can save area without causing performance loss. For rapidly changing processors, it can provide a direct and flexible interface to support all kinds of processors.